GATE CSE 2022
Q1.
Consider the resolution of the domain name www.gate.org.in by a DNS resolver. Assume that no resource records are cached anywhere across the DNS servers and that iterative query mechanism is used in the resolution. The number of DNS query-response pairs involved in completely resolving the domain name is .Q2.
Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X, either from S or from R. S is a 1024-word memory segment and R is a 32-word register file. Based on the value of mode bit M, T selects an input word to load in X. P and Q interface with the corresponding bits in the code word to choose the addressed word. Which one of the following represents the functionality of P, Q, and T?Q3.
What is printed by the following ANSI C program?#include < stdio.h > int main(int argc, char *argv[]) { int a[3][3][3] = {{1, 2, 3, 4, 5, 6, 7, 8, 9}, {10, 11, 12, 13, 14, 15, 16, 17, 18}, {19, 20, 21, 22, 23, 24, 25, 26, 27}}; int i = 0, j = 0, k = 0; for( i = 0; i < 3; i++ ){ for(k = 0; k < 3; k++ ) printf("%d ", a[i][j][k]); printf(" \n"); } return 0; }Q4.
What is printed by the following ANSI C program? #include < stdio.h > int main(int argc, char *argv[]) { int x = 1, z[2] = {10, 11}; int *p=NULL; p=&x *p=10; p =&z[1]; *(&z[0]+1)+=3; printf("%d, %d, %d \n",x,z[0],z[1]); return 0; }Q5.
Suppose a binary search tree with 1000 distinct elements is also a complete binary tree. The tree is stored using the array representation of binary heap trees. Assuming that the array indices start with 0, the 3rd largest element of the tree is stored at index _______.Q7.
Consider a system with 2 KB direct mapped data cache with a block size of 64 bytes. The system has a physical address space of 64 KB and a word length of 16 bits. During the execution of a program, four data words P, Q, R, and S are accessed in that order 10 times (i.e., PQRSPQRS...). Hence, there are 40 accesses to data cache altogether. Assume that the data cache is initially empty and no other data words are accessed by the program. The addresses of the first bytes of P, Q, R, and S are 0xA248, 0xC28A, 0xCA8A, and 0xA262, respectively. For the execution of the above program, which of the following statements is/are TRUE with respect to the data cache?MSQQ8.
A cache memory that has a hit rate of 0.8 has an access latency 10 ns and miss penalty 100 ns. An optimization is done on the cache to reduce the miss rate. However, the optimization results in an increase of cache access latency to 15 ns, whereas the miss penalty is not affected. The minimum hit rate (rounded off to two decimal places) needed after the optimization such that it should not increase the average memory access time is _____.Q9.
The value of the following limit is _____ \lim_{x \to 0+} \frac{ \sqrt{x}}{1-e^{2 \sqrt{x}}}Q10.
Let WB and WT be two set associative cache organizations that use LRU algorithm for cache block replacement. WB is a write back cache and WT is a write through cache. Which of the following statements is/are FALSE?MSQ